In electronic systems, there is often a need to control the timing of events. Within a single integrated circuit (e.g., a chip) this may be accomplished by providing an external clock signal or by generating a clock signal internally. When events in multiple circuits need to be coordinated, the same clock signal may be provided to the multiple circuits. Due to variations in the circuits and paths of the clock signals to these circuits, the clock signals at each circuit may drift over time and need to be synchronized. Also internal circuits such as clock multiplier or divider circuits may start up with different initial conditions. In both cases, a synchronization signal may periodically synchronize these clock signals.
In order to successfully synchronize the clock signal to the synchronization signal, the timing relationship between the synchronize signal and the clock signal needs to adhere to certain timing constrains. The timing constraints may be influenced by a setup and hold time of the components performing the synchronization. The setup and hold time may define a window of time around a trigger event of the clock signal. During this setup and hold time, the synchronization signal should be stable in order for the synchronization signal to provide consistent results. If the synchronization signal is unstable during this period—if, for example, it transitions within the setup and hold time—then a component may not generate a reliable output. For example, two circuits that receive the clock and synchronization signals under the same conditions and ideally would generate identical outputs, may generate different outputs due to manufacturing differences between the circuit (process variation) or due to ambient operation conditions. To ensure that consistent results are provided, signal transitions should occur outside of the setup and hold window.
However, as clock frequencies increase, maintaining proper timing alignment between clock signals and the synchronize signal becomes increasingly difficult. This may be due to part-to-part differences among circuits and variations in the environmental factors (e.g., temperature and supply voltage) that may cause circuits to behave differently.